The present invention relates to a semiconductor integrated circuit constituted by MOSFETs and, more particularly, to a clocked driver circuit.
FIG. 4 shows a conventional clocked driver circuit. This circuit comprises a first NAND circuit 1 having first and second input terminals respectively connected to an input terminal 1 and a node 5 and having an output terminal connected to a node 3, a first inverter 2 having input and output terminals respectively connected to the node 3 and an output terminal 7, a second NAND circuit 3 having first and second input terminals respectively connected to a node 6 and an input terminal 2 and having an output terminal connected to a node 4, a second inverter 4 having input and output terminals respectively connected to the node 4 and an output terminal 8, a first resistive element 5 connected between the nodes 3 and 6, a second resistive element 6 connected between the nodes 5 and 4, a first capacitive element 7 connected between the node 5 and the ground potential, and a second capacitive element 8 connected between the node 6 and the ground potential.
FIG. 5 shows an operation of the circuit in FIG. 4.
Complementary signals indicated by 1 and 2 in FIG. 5 are input to the first and second input terminals. Assume that in an initial state, the signal 1 is at low level; the signal 2, high level; a signal 3, high level; a signal 4, low level; a signal 5, low level; a signal 6, high level; a signal 7, low level; and a signal 8, high level.
When the signal 2 as the second input is changed from high level to low level (at the same time, the signal 1 as the first input is changed from low level to high level), the signal 4 is changed from low level to high level, and the signal 5 is changed from low level to high level by an RC time constant. When the signal 5 exceeds the threshold value of the NAND circuit 1, the signal 3 is changed from high level to low level, and the signal 6 is changed from high level to low level by the RC time constant. When the signal 1 as the first input is changed from high level to low level (at the same time, the signal 2 as the second input is changed from low level to high level), the signal 3 is changed from low level to high level, and the signal 6 is changed from low level to high level by the RC time constant. When the signal 6 exceeds the threshold value of the NAND circuit 3, the signal 4 is changed from high level to low level, and the signal 5 is changed from high level to low level by the RC time constant.
The above operation is repeated to obtain the signals 7 and 8 in FIG. 5 as output signals, which are the inverted signals of the signals 3 and 4. A characteristic feature of the circuit is that when a single-phase signal having a frequency f is input, two-phase signals can be obtained as output signals which have the frequency f and do not overlap each other at high level, by changing the cycle.
In the conventional clocked driver circuit, in order to prolong an interval in which both the first and second output signals are at low level, changes in potential of the signals 5 and 6 are delayed by increasing the values of the resistive elements 5 and 6 or the capacitive elements 7 and 8 to increase the RC time constant. If, however, this RC time constant is excessively increased, the potentials of the signals 5 and 6 are not fully amplified between the power source potential and the ground potential, as shown in FIG. 6. As a result, the timings of output signals from the clocked driver circuit are undesirably changed because of fluctuations of characteristics of the resistive elements, the capacitive elements, and the MOSFETs, or noise.